The present invention relates generally to electrical circuits and, more particularly, to interface circuits, such as programmable input/output circuits.
Input/output (I/O) circuits are commonly used for transferring data to and from an integrated circuit or other type of electronic device. I/O circuits (also referred to as input/output buffers, receiver/transmitter circuits, or receiver/driver circuits) are often designed to support a specific type of I/O interface standard (e.g., low voltage differential signaling (LVDS) or high-speed transceiver logic (HSTL)) or one signal level requirement type within an I/O interface standard (e.g., a specific type of LVDS). These I/O interface standards generally address chip-to-chip interfaces, board-to-board interfaces, and box-to-box interfaces for a wide range of existing and emerging applications, such as data packet processing, data bus bridges, and high-speed memory interfacing.
For example, FIG. 1 illustrates a conventional single-ended receiver (i.e., input buffer), which receives a supply voltage (VDD) and a reference voltage (VREF), along with an input signal (IN), and provides a corresponding output signal (OUT). A current source is disposed prior to a ground voltage (VSS) to regulate the amount of current flowing through the receiver. The receiver shown in FIG. 1 is generally used for low-speed applications (e.g., up to approximately 300 MHz) for single-ended signals, such as for example HSTL, stub series terminated logic (SSTL), and gunning transceiver logic (GTL) I/O interface standards.
As another example, FIG. 2 illustrates a conventional differential receiver (i.e., input buffer), which receives the supply voltage (VDD) and an input signal (IP) and its complement (IN) and provides differential output signals (OP and ON). The current source and the ground voltage (VSS) are also shown, as discussed in FIG. 1. The receiver shown in FIG. 2 is generally used for high-speed applications (e.g., 1 GHz or higher) for differential signals, such as for example LVDS or current-mode logic (CML) I/O interface standards. Multiple stages of the receiver may be employed as shown for the high-speed applications.
It would be useful for an I/O circuit, such as shown in FIG. 1 or 2, or a bank of I/O circuits to have added flexibility, such as for example to support more than one I/O interface standard or more than one signal level requirement type within an I/O interface standard. However, providing this flexibility often leads to unwanted signal integrity issues, such as the introduction of an unacceptable level of noise, or an unacceptable level of circuit complexity. As a result, there is a need for a flexible programmable interface circuit (e.g., a programmable input circuit and/or output circuit).
Systems and methods are disclosed herein for providing a programmable interface circuit to support differential and single-ended signals. For example, in accordance with one embodiment, a programmable input circuit is configurable as a single-ended buffer or as a differential buffer. Furthermore, in accordance with another embodiment, one or more multiplexers, which are used to configure the programmable input circuit, also provide a filtering function to reduce high frequency interference and maintain signal integrity.
These techniques are also applicable for a programmable output circuit, which is also discussed herein. Thus, a programmable input buffer and a programmable output buffer, for differential and single-ended signals, are disclosed, which can be implemented, for example, in programmable logic devices (e.g., field programmable gate arrays or complex programmable logic devices) or designed as part of an application specific integrated circuit.
More specifically, in accordance with one embodiment of the present invention, an interface circuit includes a first input buffer having a first and a second input lead, wherein the first input lead is coupled to a first terminal; a plurality of reference buses adapted to provide reference signals; a first multiplexer, coupled to the plurality of reference buses, adapted to provide one of the reference signals from the plurality of reference buses as its output signal; and a second multiplexer, coupled to the first input buffer and the first multiplexer, adapted to provide to the second input lead the output signal from the first multiplexer or an input signal from a second terminal.
In accordance with another embodiment of the present invention, an integrated circuit includes a first input buffer having a first and second lead, wherein the first lead is coupled to a first terminal; a second input buffer having a third and fourth lead, wherein the fourth lead is coupled to a second terminal; means for providing a plurality of reference signals; means for providing one of the plurality of reference signals to the second lead of the first input buffer or coupling the second lead to the second terminal; and means for providing one of the plurality of reference signals to the third lead of the second input buffer or coupling the third lead to the first terminal.
In accordance with another embodiment of the present invention, a circuit includes a multiplexer having a plurality of pass transistors; and a capacitor coupled to the multiplexer, wherein a resistance for at least one of the pass transistors is determined to provide, in combination with a capacitance provided by the capacitor, a lowpass filtering operation for a signal passing through the at least one pass transistor.
In accordance with another embodiment of the present invention, a method for receiving differential and single-ended signals includes providing a differential input buffer having a first and second input lead; coupling a first input signal path to the first input lead; and providing a configurable path to the second input lead, wherein the configurable path can be configured to provide a second input signal path to the second input lead or configured to provide a reference signal path to the second input lead to receive a desired reference signal.
The scope of the invention is defined by the claims, which are incorporated into this section by reference. A more complete understanding of embodiments of the present invention will be afforded to those skilled in the art, as well as a realization of additional advantages thereof, by a consideration of the following detailed description of one or more embodiments. Reference will be made to the appended sheets of drawings that will first be described briefly.